This invention is related to integrated circuit manufacturing in general and, more particularly, to the testing and/or configuration of the integrated circuit product dies or die-lets, small dies, on a semiconductor wafer.
Integrated circuit products are formed by multiple patterns of different material layers in, at, and on the surface of a semiconductor wafer. The same patterns are repeated over the surface of the semiconductor wafer which is then cut by a scribing saw in a dicing operation to separate the patterns of material layers. Each piece of the wafer with its pattern of material layers is a integrated circuit product die or die-let, both hereafter termed as a die-let.
While still part of the wafer, the die-lets are tested by connection to a test circuit or product set-up circuit, which tests and/or electrically configures the die-let for correct operation. Then the wafer is scribed or sawn in a dicing operation to separate the die-lets. Each separated die-let should be able to function in its configured state without any further electrical connection to the test circuit which had originally electrically configured the die-let.
During the dicing operation, the electrical connections between the test circuit and the die-lets are physically cut. Ideally these severed signal lines, typically formed from metal layers, should not interfere in any way with the normal operation of the die-let. However, the cutting process may not guarantee that the cut lines are totally isolated electrically. Electrical leakage at the cut line may interfere with the correct operation of the die-let.
Therefore, it is desirable that the die-lets be immune from the effects of the dicing operation in some manner. The present invention provides such a solution.